The present invention relates to display technology, and more particularly, to a shift register unit, a gate driving circuit and a display panel.
With the continuous development of display technology, a display device such as an Organic Light Emitting Diode (OLED) display device has been increasingly used in high performance display field due to its small volume, low power consumption, no radiation, and low manufacturing cost.
Within the effective display area of a display panel of such a display device, there is provided pixel cells arranged in a matrix defined by intersecting a plurality of gate lines and a plurality of data lines. The peripheral area of the display panel is provided with a gate driving circuit for conducting a line-by-line scan on the gate lines. Through a line-by-line scan, the pixel cells are turned on line-by-line, and then the turned on pixel cells may be charged through the data lines. The current gate driving circuit usually integrates a gate switch circuit of a Thin Film Transistor (TFT) onto the display panel by means of a Gate Driver on Array (GOA) technology.
In recent years, the display panel has evolved towards large size, high resolution and high frame rate. However, as the size and resolution of the display panel increases, the number of the pixel cells in each row and each column on the display panel will increase accordingly. In this case, if frame rate is increased, scanning time for pixel cells in each row will be reduced, thus charging of the pixel cells will be insufficient.
For this reason, a solution has been proposed in which a plurality of clock signals are connected to a plurality of shift registers such that the scanning signals of two adjacent rows overlap with each other to pre-charge the pixel cells. Furthermore, by changing the internal structure of the shift registers and adjusting the clock signals, the width of the overlapped region can be changed. However, the wider the overlapped region is, the more the clock signals are required to be connected to the shift registers. Thus, the area for deploying the gate driving circuit is increased, and the complexity of the display panel is increased, which is not advantageous to achieve a narrow frame of the display panel.